Confronting the Challenges of Nanometer Design
A common precept, one currently under scrutiny in the semiconductor industry, is the belief that smaller is better. As long as there has been a semiconductor industry, each new generation of chips has been characterized by a drive for finer features. Finer features drove increased integration, integration enhanced the functionality that could be delivered, and that, in turn, lowered the cost of manufacturing.
Physical design and technology development worked in synergy to bring this about. Each technology node not only had smaller critical dimensions and new materials, but also other density-improving optimizations, such as “dogbones” on vias disappearing at the 180nm node, significantly decreasing routing half pitch. Each new node resulted in new library developments to take advantage of these specifications. The result-smaller, faster, cheaper chips.
What’s clear is that nanometer technology has the potential to forever alter this course. The 130nm node, early optimistic reports not withstanding, was very difficult to bring up. Signal integrity, power requirements, resolution enhancement, and resistive-type defects were just a few of the issues formerly relegated to the background that began taking center stage. These formed the foundation for the new world of design for manufacturing (DFM).
Please disable any pop-up blockers for proper viewing of this Whitepaper.