Confronting Chip Assembly Challenges: Avoid Late-Stage Bottlenecks in Physical Design
The increasing size and complexity of today’s multi-million gate SoCs necessitates hierarchical chip design methodologies, which partition the chip into smaller pieces. A hierarchical methodology is necessary for large SoCs because it extends the capacity of design-automation tools, improves tool runtimes, and limits last minute design changes. However, even hierarchical flows using the current-generation of physical implementation tools are facing problems closing the chip requirement within aggressive schedules. In this paper, we review chip assembly challenges and discuss the requirements of an implementation system that comprehensively addresses all the issues.
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