Eye patterns (EPs) are used in high speed digital systems as a metric of electrical performance and are generated by superimposing multiple data bits on the same diagram. Timing and amplitude margins are two parameters which can be extracted from an eye diagram provided chip thresholds for jitter and amplitude are known.

In this report we examine passive interconnect in terms of EPs where the EPs are generated using two different methodologies. The first method uses HSPICE from Synopsys, a commercial non-linear time domain simulation tool. The second method uses frequency domain data measured with an Agilent E864B Network Analyzer. This measured data is transformed into the time domain and viewed as an eye pattern using Agilent Physical Layer Test System (PLTS) version 2.5 software. A Samtec Final Inch QPairs QTE-DP/QSE-DP Test and Evaluation Board, with 5mm stack height connectors, is used as the basis for the HSPICE simulations and the network analyzer measurements