The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins. Low pin count testing (LPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying LPCT, devices can be easily tested on structural DFT testers at dramatically reduced costs while meeting the low pin count requirements of device and design flow. Combining LPCT with test compression further extends the test capabilities to allow application of all necessary fault models using low-cost testers that are seriously pin-limited. The techniques described here enable gains in test coverage with less application time and minimal effects on design and test overhead.

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