There are some clock devices well-suited to meet the demands for high-speed ADC devices that are capable of sampling up to 210 MSPS. To realize the full potential of these high-performance devices, it is imperative to provide a low phase noise clock source. A real-world clocking solution meets these stringent requirements for high-speed ADCs. This application report highlights the limiting agents associated with the clock source that adversely affect the ADC signal-to-noise performance.