Extremely high-speed analog-to-digital converters (ADCs) (>1 GSPS) demand a low-jitter sample clock in order to preserve Signal-to-Noise Ratio (SNR). These 8- and 10-bit converters have best-case noise floors set by quantization noise. For an N-bit ADC sampling a full-scale sinusoid, the well-known expression for SNR (in dB) is: SNR = 6.02N + 1.76. This sets the best case noise floor for an 8-bit ADC at -49.9 dBc. The noise floor degrades from this point on due to factors such as jitter on the sample clock, intrinsic aperture jitter of the ADC, spurious components arising from non-linearities in the ADC quantizer, and other internal noise such as thermal noise.

This application note looks at a strategy for optimizing the performance of a sample clock based on PLL/VCO characteristics. This means minimizing overall integrated phase noise, which minimizes clock jitter.