As FPGAs grow in size, quality on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact device performance; managing clock skew and clock delay with conventional clock trees becomes more difficult in large devices.

Traditionally, you would deploy solutions such as a Xilinx Virtex-4 digital clock management (DCM) or mixed-signal phase-locked loop (PLL) to achieve clock tree deskew and frequency synthesis, among other functions. Yet each solution has its advantages and disadvantages.

Reprinted with permission from Xcell Journal / Fourth Quarter 2006. Article © Xcell Journal.