Clock jitter analyzed in the time domain, Part 1
Newer high-speed ADCs come outfitted with a large analog-input bandwidth so they can be used in undersampling applications. In the design of an undersampling receiver, special attention has to be given to the sampling clock, because at higher input frequencies the jitter of the clock becomes a dominant factor in limiting the signal-to-noise ratio (SNR). Part 1 of this three-part series focuses on how to accurately estimate jitter from a clock source and combine it with the aperture jitter of the ADC. In Part 2, that combined jitter is used to calculate the ADC’s SNR, which will then be compared against actual measurements.
Please disable any pop-up blockers for proper viewing of this Whitepaper.