With the growing trend toward use of systems-on-a-chip (SOCs), designs with multiple asynchronous clock domains are becoming commonplace. With the emergence of asynchronous clock domain crossing (CDC) verification tools, users have a way to verify their designs. However, first generation CDC tools do not provide adequate support for a top-down, bottom-up CDC verification methodology; also, extensive manual
setup and signoff requirements create serious deployment limitations. This causes inconsistent usage of the tools and wasted engineering resources without
covering the CDC failure risk.


This paper describes an efficient, reliable and practical CDC verification methodology for effective timing closure verification (TCV).