This white paper will show you how to substantially secure the bitstream and the overall design of FPGAs using Xilinx CoolRunner™-II CPLDs. It will not particularly address Virtex™-II and its successors because they already employ Triple DES bitstream encryption, which is considered by many to be sufficiently strong encryption to deter IP theft. It will rather focus on volatile FPGAs in general, including both Xilinx FPGAs and competitors’ FPGAs within its scope.