In the electronics industry, the term “process shrink” is often used to refer to when a semiconductor company migrates an existing design to a smaller process technology. In many cases, this is an upgrade path for reducing the cost, size, and power consumption of chips. An example of a “simple” process shrink is that of Texas Instruments’ 720-MHz TMS320C6416 DSP. Moving the C6416 DSP from a 130-nm CMOS process to 90-nm resulted in a price reduction of 50 percent.

If this were the end of the story, it would still be impressive. However, this only describes a single facet of the changes that must come when a new process technology is introduced. A process shrink alone will not enable you to keep pace with Moore’s Law. To achieve the greatest gains, it is necessary to innovate in several dimensions simultaneously. To only claim the advantages of a smaller die is to ignore the new levels of SoC integration enabled by finer geometries. The real excitement starts when designers are able to integrate divergent technologies in ways never before possible.