Challenges to Silicon Modeling in the Nanometer Era
The nanometer era has revealed significant concerns in signal integrity and timing closure in analog mixed signal designs. Physical effects are now the leading factor in the failure to achieve acceptable yield. A combination of factors that emerge in nanometer scale ICs, such as shrinking feature sizes, finer line widths, longer interconnect, more routing layers and more analog content, have a profound effect on the ability to gain acceptable levels of yield. Traditional methods of black boxing, assumptive device measurement and gate-level extraction are not sufficient to meet the accuracy requirements of simulating sophisticated IC designs. This is a task that can only be accomplished through exacting detail-actual device measurement and transistor-level parasitic extraction-evaluated across the characteristics of the entire design.
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