Catapult C Synthesis Addresses RTL Bottleneck in Ericsson's ASIC Design Flow
In this extensive case study you will see how Catapult C Synthesis addresses the classic RTL bottleneck faced by Ericsson’s ASIC design teams. Ericsson discusses existing design challenges using traditional RTL design flows and barriers they face. The case study discusses how Ericsson was able to perform frequency exploration on a wider micro-architecture design space. Ericsson discusses how this new approach yielded designs which were 20-30% smaller than hand coded methods when running at the same design latency.
Please disable any pop-up blockers for proper viewing of this Whitepaper.