Capturing Design Intent and Evaluating Performance with SystemC
Embedded development tools often focus on the implementation of a system and do not provide system architects with a suitable framework with which to explore micro-architectural, system-level trade-offs. By describing a system using a series of models, communicating at a transactional level of abstraction, simulations of systems can be rapidly created. Bus-level abstraction further allow simulations to execute much more efficiently than at the implementation-level, but with enough detail to identify effects such as bus contention. We will demonstrate a methodology for describing complete systems rapidly and efficiently in SystemC. The simulation models created using this methodology allow system architects to evaluate large amounts of complex software on their architectures before committing to an implementation. A scalable verification strategy is also presented to ensure that the specified design matches later system implementation, providing both a software and verification development platform.
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