FPGA-based prototyping is popular because it provides an economical way to functionally validate an ASIC design by creating a prototype that runs “at speed”, includes real world I/O, and enables early software development. Experienced prototypers are familiar with its benefits but there are still designers opposed to physical prototyping for a number of reasons. These are all myths rooted in the struggles of developing in-house prototypes with limited automation software of years past. This white paper busts these myths by showing that physical prototyping is low risk for almost any ASIC design validation and software development task.