Power is a demanding system design consideration today. New technology advancements, proliferating I/O standards (LVDS, LVPECL, HSTL, SSTL, etc.), legacy support requirements, and the relentless drive to design lower-power systems require most applications to use a mix of power supply and I/O drive voltages. Today’s lower-power devices have to work in this ecosystem with the older, higher-voltage devices, requiring solutions that interface with the multiple voltages that are in widespread use. This traditionally has been managed by level-translator integrated circuits (ICs), but they do not necessarily provide the flexibility to support simultaneous translations to different voltages or I/O interface standard. They also can add unnecessary cost and complexity if the system already contains an FPGA on board.

As FPGAs have become a more popular design alternative for system flexibility and time to market, they also have become sensitive to power-design considerations by supporting multiple voltage options for I/O banks. This paper will examine how some low-power FPGAs leverage the VCCI of each I/O bank to determine the voltage level of its I/Os, ranging from 1.2 V up to 3.3 V. This flexibility, in turn, gives system engineers more choice in designing cost-effective, power-nimble applications that need to live and function well in a complex multi-voltage world.