In the last few years, the Optical Internetworking Forum’s (OIF) system packet interfaces (SPI) for 2.5 Gb/OC-48 (SPI-3) and 10 Gb/OC-192 (SPI-4.2) have become the de-facto standards on all leading framer ASSPs. The SPI interfaces have also permeated into the network processor’s space, including next-generation processors such as Intel’s IXP2800 and IXP2400. Although these interface standards have been widely adopted, they pose significant design challenges to the system architect under pressure to deliver a fully compliant solution where time to market is paramount. Xilinx® Virtex™-4 architectures provide an ideal platform for implementing these multi-gigabit system packet interface applications.

Reprinted with permission from Xcell Journal / Third Quarter 2005. Article © Xcell Journal.