This white paper explains the basic PCB layout guidelines for designing low-voltage differential signaling (LVDS) boards using Altera FPGAs. LVDS is a high-speed, low-voltage, low-power, and low-noise general-purpose I/O interface standard. The low-voltage swing and differential current mode outputs significantly reduce EMI. These outputs have fast edge rates that cause signal paths to act as transmission lines. Therefore, ultra-high-speed board design and differential signal theory knowledge is especially useful for designing a board containing Altera FPGAs that integrate LVDS. In addition, a number of factors, such as differential traces, impedance matching, crosstalk, and EMI, have to be considered while designing an LVDS board.