I’ve seen a lot of experienced folks stumble with the blocking vs. non-blocking statements in Verilog. Engineers spend a large amount of time debugging the simulation dumps and trying to understand why race conditions are occurring and how they shall be solved. Further there are times when the issue is solved in one simulator; however, the code behaves differently on another simulator. Another scenario is the issue gets solved in one simulator and fails at the customer’s end using the same simulator, as the test environment changes. This often happens as some engineers tend to rely on a code that uses scheduling, where results can be indeterminate.