This paper addresses a family of turbo codes called “block turbo code,” based on iterative decoding of product codes. In the first part of the paper, the concept of product code and soft iterative decoding are introduced, and simulation results are discussed. The iterative decoding process is then illustrated with an example and the flexibility of block turbo codes, important for practical applications, is considered.


The second part of the lecture is dedicated to implementation of the code on an FPGA or ASIC. Simplifications of initial algorithm and trade-off between complexity and performance are considered, as are several architectures.