Binding SystemVerilog to VHDL Components Using Questa
Binding SystemVerilog to VHDL Components Using Questa SystemVerilog offers a rich set of testbench automation capabilities, native assertions, and functional coverage. These features make SystemVerilog increasingly appealing to VHDL users who need to implement an efficient and effective functional verification methodology. The Questa advanced verification environment offers native support of SystemVerilog, Verilog, and VHDL, making it easy to adopt SystemVerilog.
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