Beyond P-Cell and Gate-Level Assumptions: Accuracy Requirements for Simulation of Nanometer Designs
The forward march of Moore’s Law has resulted in integrated circuit (IC) designs containing more and more functionality on a single chip. While nanometer technology enables expanded capability, such as analog-mixed signal systems-on-chip (AMS SoC), it brings with it a new set of design closure problems. Complex designs demand more power and higher clock frequencies; they also create more signal and power net electromigration and substrate noise. The stress effect of a single analog device with unique diffusion measurements can cause an entire chip to fail. This is a huge problem for designers; half of all AMS designs fail first silicon. With mask costs reaching $1 million each, designers can no longer afford to rely on parameterized cell or gate-level parasitic extraction assumptions for analysis and simulation. Nanometer-era designs require accurate and comprehensive data to enable accurate modeling.
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