Smart devices and smartly-connected IoT devices, cloud computing and big data, device integration and fabrication technology all continue to drive power budgeting, energy and thermal efficiency for IP and SoC semiconductor design. Early visibility to power can drive power-related architectural design decisions early in the flow for the highest impact. Managing power at RTL (Register Transfer Level) has emerged as a reliable, high-performance, high-coverage, and high-capacity alternative to traditional gate-level netlist based power methodology. This paper focuses on designing power-efficient RTL through a set of prevalent best practices including early power budgeting, analysis, reduction and regressions.