Factors like jitter, inter-symbol interference (ISI), crosstalk and others can create havoc on the signal integrity of high-speed serdes and memory channels, making maximum bus speeds difficult to achieve in practice. Compounding this predicament is the fact that channel speeds keep increasing from one generation bus technology to the next. To avoid potential problems with high-frequency bus traffic, the signal integrity on the bus must be validated during each of the major phases of a system’s life cycle. If the signal integrity on a serdes channel is not what it should be, steps should be taken to correct the problem and improve system performance.