AXI4 Interconnect Paves the Way to Plug-and-Play IP
In the past decade, the size and complexity of many FPGA designs exceeds the time and resources available to most design teams, making the use and reuse of Intellectual Property (IP) imperative. However, integrating numerous IP blocks acquired from both internal and external sources can be a daunting challenge that often extends, rather than shortens, design time. As today’s designs integrate increasing amounts of functionality, it is vital that designers have access to proven, up-to-date IP from reliable sources. Two key enablers, the creation of plug-and-play IP and the expansion of the ecosystem, have been significantly advanced with the release of the Advanced Microcontroller Bus Architecture (AMBA4) AXI4 interconnect standard and its subsequent availability in Xilinx ISE Design Suite, version 12.3.
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