Over 40 percent of field programmable gate array (FPGA) design projects fall behind schedule. In order to reduce risk of delay of product delivery, changes need to be made not just in verification, but also in the design process itself. Design simplification must be a principle that starts at the beginning of the project life cycle—before verification of complex code has become the bottleneck that delays project delivery.

This paper examines two concepts that can simplify the implementation of a complex FPGA design: the use of SystemVerilog and vendor-independent modeling.

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