As designs become more complex and previously independent functions become integrated on a single chip, chips with multiple asynchronous clock domains are becoming the norm. Signals that cross between these domains, called clock-domain crossings (CDCs) can result in metastable operation, which often causes intermittent chip failures that can go undetected until the chip is in the lab or even operating in the field. This poses a serious risk to safety in system operation, and is driving the adoption of CDC verification tools.


This paper introduces the issues concerning CDC, how to verify CDCs in order to avoid inadvertent design failures, and how to use 0-In CDC on DO-254 projects.

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