Automated Yield Enhancements Implementation on full 28nm Chip: Challenges and Statistics
This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved , e.g., at mask data preparation. It discusses and presents the algorithm used to measure the efficiency of the tool, explaining why we used this algorithm while sharing some alternate algorithms possible. The paper also shares the detailed statistics regarding run time, machine resource, data size, and polygon counts. Finally, good techniques used by us for efficient flow management involved in large complex 28nm chips are presented.
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