In a SoC design involving placement of digital logic,the addition of Decaps helps in keeping the Dynamic Voltage Drop (DvD) within the characterization limits avoiding any timing violations and functional failures in the design. Using EDA tools available to perform DvD analysis and give us the amount of decap to be added, this paper describes an effective method to ensure that this requirement is met by ensuring addition of decaps in hotspots. In case of non availability of white space in those regions, non-timing critical cells are moved from these regions to lesser congested neighbors for creation of white space for these decaps ensuring fully automated removal of hotspots from the design.