Automated FSM Error Correction for Single Event Upsets
FPGAs are increasingly being used for mission-critical applications in hazardous operating environments (space, military, medical etc.). In these applications, the circuit must be fault-tolerant, especially finite state machines (FSMs), where failures are very hard to detect. Most single-fault-tolerant FSMs are implemented using triple module redundancy (TMR) or by using a single-error-correcting (SEC) code during state encoding. Typical instances of SEC employ a minimal encoding scheme to force a Hamming distance of three. Commercially available FPGA synthesis tools only implement error recovery to a specified recovery state. They do not implement error correction.
In this paper, we investigate a general technique of adding Hamming error checking bits to any encoding style of FSMs to automatically recover from single event upsets (SEUs) within the same clock cycle. We shall report on the efficacy of this method to correct single-bit errors and detect two-bit errors. Area and delay results of using this technique on selected designs are also explored.
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