Automated FPGA to ASIC Conversion with Zero NRE
FPGA design suits a fast time-to-market product, while its chip cost is high. ASIC design or traditional FPGA to ASIC design involve high resources cost, while the chip cost is low. FPGA cost overheads are tackled by addressing three aspects: redundant die area, pricing of various fab process and production material. Mainly, there are two FPGA to ASIC solutions: traditional full RTL flow to standard-cell ASIC and to Structured ASIC. KaiSemi presents a third solution: an automated conversion flow to standard-cell ASIC. The paper analyzes the risks, complexity, lead-times and costs involved with FPGA and FPGA-to-ASIC conversion options.
Please disable any pop-up blockers for proper viewing of this Whitepaper.