As In AOP So In OOP: A Transition Guide to SystemVerilog for the eUser
For e users, Aspect Oriented Programming (AOP) is a known, good mechanism for modifying, adding, or inserting functionality to a class. Fortunately, these goals can be easily achieved using Object Oriented Programming (OOP) techniques in SystemVerilog. The difference isn’t that great, so the learning curve presents a gentle gradient.
Via comparison and code examples, this paper shows how a Specman e user can easily modify an object using SystemVerilog OOP. First we’ll review a few programming basics, then compare how e and SystemVerilog handle abstract factory patterns in order to demonstrate how easy it is to replicate the AOP functionality of e in SystemVerilog OOP. We’ll conclude the paper with a complete plug-and-run OOP code example.
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