One of the major barriers for Semiconductor IP commercialization is to provide evidence for an IP’s quality. A common approach by IP vendors is to prove the quality of their IP in a test chip. Usually the Die contains the IP block separated from the System-on-a-Chip (SoC). It is, though, uncertain how the block will function in ASSP and ASIC products, potentially damaging its perceived commercial value.

In Rosetta’s methodology, the IP Core is a block within a subsystem, integrated to enable the subsystem functionality and targeted for a specific market and application. By analyzing the specific requirements of the market and application, and by providing an IP package targeted at those requirements, we solve and mitigate the IP quality