Analysis of Floating-point DSP Design Flow and Performance on Altera 28-nm FPGAs
Case Study
This paper discuses an independent analysis of Altera’s floating-point DSP design flow. BDTI’s objective was to assess the performance that can be obtained on Altera FPGAs for demanding floating-point DSP applications, and to evaluate the ease-of-use of Altera’s floating-point DSP design flow.
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