Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
The entire system-clock signal chain must be understood in order to achieve optimal performance from an Analog-to-Digital (A/D) converter. It can be discouraging to find that a circuit’s accuracy is clock-jitter limited, as this problem could have been prevented during the design phase. This article considers the relevant clock specifications and means
of achieving the expected performance of a high speed converter. It explains how decreased clock jitter can be achieved through frequency division, filtering, use of an improved clock source, and proper choice of auxiliary hardware.
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