In this paper, we discuss the design of an efficient filter bank design using residue number system. The whole computation is done using residue arithmetic. The channeliser architecture can be divided into three different sections, the filtering block, time aliasing and the Inverse Discrete Fourier (IDFT) transform block. All the necessary computations for the blocks are done based on residue arithmetic rather than using a binary arithmetic. Since the computations are in residue domain the overhead for the conversions is reduced to a minimum. We also propose a high-speed error detecting mechanism by representing the residue numbers in 1-out-of-n code form Using 1-out-of-n code, error detection is achieved without any redundant moduli. The proposed design exhibits VLSI efficient layout, operand independent delay and low power consumption.