An Overview of Methods for Increased Gate Level Compilation Efficiency
The compilation effort for gate level simulations becomes more complicated as design size increase. If the testbench is compiled alongside the design, this means every change in stimuli or testing environment requires re-compilation and a loss of valuable time and resources, complicating the development stage. There are several solutions to this problem, separate compile, the use of small sub environments and the use of master stimulus as will be described in this paper.
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