An Integrated Tool Flow Supporting FPGA Prototyping and Debug
As electronic systems grow larger and more complex, designers face new and increasing challenges in the design, verification, implementation and fabrication of those devices. This paper focuses on two of those challenges: the decreasing visibility of large integrated systems, be they in an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA), and the increasing number of bug escapes that result from a simulation-only verification flow. Those challenges can be solved by a design-for-debug (DfD) tool suite coupled with an optimizing compilation system — a combination that provides a fast, efficient, and flexible solution.
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