Altera has developed a new floating-point design flow intended to streamline the process of implementing floating-point digital signal processing algorithms on Altera FPGAs, and to enable those designs to achieve higher performance and efficiency than previously possible.  BDTI performed an independent analysis of Altera’s floating-point DSP design flow. BDTI’s objective was to assess the performance that can be obtained on Altera FPGAs for demanding floating-point DSP applications, and to evaluate the ease-of-use of Altera’s floating-point DSP design flow. This paper presents BDTI’s findings, along with background and methodology details.