Multiple data rate memories are now common for dynamic (SDRAM) and non-volatile (Flash) type memories. Typically, these are implemented with a double data rate (DDR) protocol and interface that provides source synchronous data and clock and/or data strobe. But the protocol used for the transfer of data between the memory controller and memory is not symmetric with respect to the direction of data transfer. Write operations to memory from the controller allow easy acquisition of the data by the memory device, but this is not the case for read operations from the memory to the controller. Presented here is a proposal for improving this protocol.