An Evolution of Gate and Via Parasitic Resistance Extraction
Cypress has recently modified the parasitic resistance extraction of Vias and Gates. Rather than use a hard number for pex via reduction count for Via grouping, we have found that using flexible pex via reduction resistance for all layers and allowing user specified application of the “standard count” modifier provides nodal reduction and the ability to increase accuracy if needed. For transistor devices, Cypress extracts parasitic resistance to the center of the seed layer, one half the width of gate. Gates only contacted on one side omit one half of the resistance. Experiments have shown that a more accurate estimation is one third. To achieve that accuracy, our flow now uses resistance device seed to lower poly resistance. Capacitive accuracy is maintained by treating the gate device as poly a equivalent through the use of capacitance alias. This paper presents details on the evolution of our parasitic resistance flow.
Please disable any pop-up blockers for proper viewing of this Whitepaper.