An automated method to generate isolation values in Low power design
Dynamic and static power gating is one of the most popular methods used in the industry to reduce power of SoC. These complex techniques include introduction of various level-shifters, retention-cells and isolation cells for the signals crossing from off domain to on domain and vice versa. At present, the isolation cell’s inactive values are generated manually in the design phase. The erroneous values of any of these isolation cells can introduce fatal bugs in design. This paper proposes a method to generate these isolation values automatically which can be fed directly to CPF/UPF (power intent file), which in turn insert proper isolation cells for each power domain crossing signals.
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