As IC technology approaches 10 million+ gates per chip, it is widely recognized that large portions of new ASIC designs must leverage pre-existing designs in order to avoid unacceptably long development schedules. Committees and user groups have begun to form to define IP implementation, usage, and delivery standards. Synthesizable IP, or soft IP, is by far the most flexible in terms of providing a path for migration to next. However, to be of use in the fast moving digital communications area, soft IP must also possess functional flexibility to keep up with algorithm advancements and evolving multiple standards. Parameterization mitigates the main problem with most currently available soft cores – the inability to adjust them so they fit into a specific design. Parameterized IP offers the ability to tailor the functionality and performance of the core over a multitude of applications.

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