Designers no longer have the large timing margins they once had when chip delays consumed the bulk of overall timing budgets. Since then, timing margins were generally sufficient in almost all cases. Die sizes and component geometries have decreased and the propagation delays through these devices have diminished significantly.

With this trend has come a dramatic increase in clock rates used at the board level. The technologies for creating the majority of printed circuit boards, despite the adoption of many manufacturing innovations, has remained mostly unchanged. The decrease in interconnect delays due to board size has not come on the same order of magnitude as the shrinking and increased clock speeds prevalent in the many components in use today. As a result, board level interconnect delay accounts for a much larger percentage of the overall timing budget, which has resulted in a dramatic decrease in the overall timing margins of designs.

Incorporating accurate timing margins under extreme conditions, and understanding specific timing sensitivities in the circuit, ensures robust system operation. Eliminating timing problems as early in the design cycle as possible reduces-and may even eliminate-multiple design iterations and costly rework.

This article explores device-timing alternatives that allow for the most effective combination of devices while ensuring that the design still meets performance goals. We see that using circuit netlists with symbolic timing models provides a repeatable mechanism that easily accommodates circuit connectivity changes, explores device variations and guarantees correct net connectivity during analysis.

Further, symbolic timing allows circuit designers to explore, understand and validate the timing requirements of your circuit. These requirements can drive physical routing to provide a complete timing solution.

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