Advanced ROM to RAM Inferencing in Precision Synthesis
ROM decoding can create multiple levels of logic in an FPGA design. Not only could this result in critical timing paths and other problems, but your runtimes may also suffer. It is essential for a synthesis tool to take advantage of rich FPGA RAM architectures. This application note shows how smart ROM inferencing, combined with advanced ROM to Block RAM mapping algorithms, provides a powerful synthesis solution for designing with today’s advanced FPGA memory hardware architectures.
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