Nanometer designs have not only grown in density and function, but also in data volume; a single systems-on-chip (SoC) design can produce a file size larger than 12 gigabytes. Although large designs allow greater functionality and performance for the end user, for the designer they can be unmanageable. During the important full chip verification and chip finishing stage, a 12-gigabyte design can take hours to open for viewing and editing. Since there are generally several iterations done during this chip finishing stage, this not only forces down time-unproductive hours-but can also greatly affect a project schedule, especially at the time-sensitive back end when the project deadline is near. This paper presents a case study of one semiconductor company’s efforts to address the problem. It suggests current tools that address many chip finishing needs, and provides an example of a chip-finishing methodology that designers can easily integrate into their own design tool flows using Calibre® DESIGNrev.

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