Memory designers need to increase bit density to meet exacting specifications for fast data transfer and low power consumption. Higher density increases the interactions between interconnect and devices, yet they have to design with real design margins. Accurate characterization is required at every step of memory design. Memory designers need a tool that can help them analyze parasitic issues accurately and quickly at every stage of the physical design cycle, as well as design cutting-edge memories from basic building blocks to the full chip. Using Calibre xACT 3D at all stages of memory design, from bit cell design to full chip sign-off, ensures a robust design that will work to specification when it is manufactured.

Note: By clicking on the above link, this paper will be emailed to your EE Times log-in address by Mentor Graphics.