Functional verification consumes the largest portion of development time for many system-on-a-chip (SoC) design projects. The traditional approach of writing black-box, end-to-end simulation tests is not sufficient for finding corner-case bugs deep in the design. Formal verification — the alternative to simulation — though its thoroughness is effective, has limitations as well. A new white-box verification technique called “semi-formal verification,” on the other hand, combines traditional simulation with formal technology, in order to deliver the advantages of formal verification without its disadvantages.


This paper discusses functional verification of register-transfer-level (RTL) hardware descriptions, introducing the semi-formal verification method.