Advanced electrical rule checking in IC reliability verification
Traditional electrical rule checking (ERC) verifies simple electrical design rules, such as floating wells and bad device construction, using basic connectivity and device information. However, more complex ERC circuit issues are now being checked, including latch-up, noise immunity, floating pins, crosspower-domain verification, and leakage current, among others.
With advanced semiconductor process technology, the introduction of the system-on-chip (SoC), and the existence of multiple power domains in today’s designs, ERC has become more and more challenging, to the point where traditional EDA tools are no longer sufficient because of the in-context information required by many of these ERC checks.
In this paper, read about an EDA tool with the ability to combine electrical and physical attributes to provide advanced automated circuit verification for electrostatic discharge (ESD), electrical overstress (EOS), multiple power domains, advanced ERC, and other reliability concerns.
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