ARM design simulation models are an excellent choice for System-on-Chip (SoC) functional verification. Since they are compiled from the core’s RTL, they’re very accurate and often used for sign-off simulation. Tests written in C or assembly execute on the design
simulation model (DSM) and drive bus-cycles into the design in a manner identical to that of the actual silicon. In fact, these tests can be used in both the simulated and physical prototype arenas.


One factor limiting the deployment of DSM-driven tests is the lack of an effective debug environment. Tests written in C are often debugged with logic simulation views like the waveform trace display. DSMs lack the API and underlying functionality required to support a source-level software debugger, so debug must be done with static text files like the assembly listing and symbol table. This article presents new technology that significantly advances DSM debug. The result is a rich source-level DSM debugger that is completely non-intrusive.

Reprinted in its entirety from ARM IQ Vol. 7, No. 2, 2008